1. Field of the Invention
The present invention relates to a technique of displaying delay times of signals occurring on paths on an electronic circuit that has been designed.
2. Description of the Related Art
In recent years, the demand has increased for the ability to develop electronic circuits such as printed circuit boards (PCBs), integrated circuits, and the like in a shorter time period and at a lower cost. Thus, the importance of the CAD (Computer Aided Design) technique has also been increased because the CAD technique can assist in the development of electronic circuits.
In the CAD technique for electronics, importance is placed on standardization and modeling in order to permit user to perform design even when they do not have a vast knowledge of designing. Elements or components that serve as the functional or logical units for electronic circuits are registered as the fundamental elements (cells) in a library. Usually, fundamental gates such NANDs and NORs; sequential circuits such as flip flop (referred to as FF hereinafter) circuits, counters, and shift registers; memory units; and CPUs are registered as the cells in libraries. Therefore, logical design is performed by selecting the necessary cells from the library and connecting the selected cells to one another. The connections among the cells are realized by connecting the pins of the respective cells. The layout design is performed after performing the logical design.
On an electronic circuit that has been designed, various analyses are performed in order to confirm whether or not the electronic circuit has been appropriately designed. Timing analysis is one of these analyses. Timing analysis is performed in order to check whether or not a failure (such as a malfunction) may be caused by a time difference between the signals transmitted on the paths. Timing analysis includes the setup-time check and the hold-time check. In the setup-time check, it is checked whether or not the timing at which the FF or the like takes in data is too late. In the hold-time check, it is confirmed whether or not the timing at which an FF or the like takes in data is too early. The various analyses including timing analysis can be performed automatically.
The failures detected in the timing analysis have to be removed. For this removal, the design has to be modified. This modification is usually made in such a manner that the time differences are examined for each line between the pins included in the path on which the failure was detected, and at least one line between the pins that is to be adjusted is determined; thereafter, the delay time on the determined line is adjusted. Accordingly, designers have had to perform complicated operations for this adjustment. On the basis of this situation, it can be thought that facilitating design modification is important.
Patent Document 1 discloses a conventional delay time display device that displays delay times existing on the predetermined path. This delay time display device displays delay times caused by the cells being connected to a fixed signal line or by the delay time difference between them. Thereby, the clock distribution circuit using fixed distribution lines is assumed, and the delay time difference (clock skew) between the clock signals distributed by the distribution circuit to the respective paths is easily understood.
The clock distribution circuit is commonly used to provide clock signals to a plurality of pins. However, a failure may occur on the path that is conveying the clock signals provided by the clock distribution circuit. The signals are also provided to at least one pin arranged on a path, and a plurality of connection destinations are set on each pin. Therefore, a great increase in the operation efficiency cannot be expected even when the delay time on a part of the paths is displayed.
For example, in a case where there is a failure of a clock skew between paths that have a section being used in common, the sections that are not being used commonly among the paths have to be modified in order to remove this failure. Accordingly, it is thought that information on the connection relationship between the paths has to be supplied in order to easily achieve high operation efficiency.    Patent Document 1:    Japanese Patent Application Publication No. 6-275719